Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual (DRM).
In addition, Cadence and TSMC delivered N3E and N4P process design kits (PDKs) and design flows to accelerate customer adoption and advance mobile, AI and hyperscale computing design innovation. Joint customers are actively designing with the new N3E and N4P PDKs, and several test chips have already been taped out, which demonstrates how Cadence solutions help customers improve engineering efficiency and maximize the power, performance and area (PPA) benefits offered by the latest TSMC process technologies.
The Cadence digital and custom/analog advanced-node solutions support the company’s Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.
Cadence worked closely with TSMC to ensure the digital full flow was optimized for TSMC’s advanced N3E and N4P process technologies. The complete RTL-to-GDS flow includes the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, QuantusField Solver, Tempus™ Timing Signoff Solution and ECO option, Pegasus™ Verification System, Liberate™ Characterization Solution and Voltus™ IC Power Integrity Solution. Additionally, the Cadence Genus™ Synthesis Solution and predictive iSpatial technology are enabled for the TSMC N3E and N4P process technologies.
The digital full flow offers several key capabilities that support the TSMC N3E and N4P process technologies, including the correlation between implementation and signoff results; enhanced via pillar support.
CDNS shares capsized $5.04, or 3.4%, to $144.07.
