QuickLogic Corporation (NASDAQ: QUIK) found its shares on the downside Thursday.
The developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, and eTopus, a leader in high-speed, low-latency, low power connectivity IP, today announced the industry's first disaggregated eFPGA-enabled chiplet template solution.
Based on QuickLogic's Australis™ eFPGA IP Generator and industry-leading chiplet interfaces from eTopus, the template delivers unprecedented design flexibility and bandwidth for high performance applications.
Unlike discrete FPGAs with pre-determined resources of FPGA LUTs, RAM, and I/Os, the disaggregated eFPGA-enabled chiplet template will be available initially as a configurable IP, and eventually as Known Good Die (KGD) chiplets.
According to this morning’s news release, “Each template will be designed with native support for emerging industry chiplet interfaces including the Bunch of Wires (BOW) and UCIe standards, enabling seamless integration with a customer's own devices. This approach enables customers to size the solution for their needs while being compatible with emerging chiplet standards.”
The initial template will use the 6nm process technology to balance performance and cost. eFPGA LUT counts will start at 200K with additional functionality available in block RAM and Digital Signal Processing (DSP) blocks. Surrounding the eFPGA core will be up to 384 Die2Die links developed by eTopus. Each link can run at 0.5/4/8/16G and is organized as a x64 block to efficiently transport ethernet, PCIe, AI/ML, and compute traffic.
QUIK shares lost 24 cents, or 3.2%, to begin Thursday at $7.16.
